The present invention generally relates to high-speed data communications. More specifically, the invention relates to an improved efficiency integrated current sink only line driver, which solves problems associated with the inherent transconductance difference between NMOS and PMOS devices.
With the advancement of technology, and the need for instantaneous information, the ability to transfer digital information from one location to another, such as from a central office (CO) to a customer premise (CP), has become more and more important.
In a digital subscriber line (DSL) communication system, data is transmitted from a CO to a CP via a transmission line, such as a two-wire twisted pair, and is transmitted from the CP to the CO as well, either simultaneously or in different communication sessions. The same transmission line might be utilized for data transfers by both sites or the transmission to and from the CO might occur on two separate lines. In this regard reference is now directed to FIG. 1, which illustrates a prior art xDSL communication system 1. Specifically, FIG. 1 illustrates communication between a central office (CO) 10 and a customer premise (CP) 20 by way of twisted-pair telephone line 30. While the CP 20 may be a single dwelling residence, a small business, or other entity, it is generally characterized as having plain old telephone system (POTS) equipment, such as a telephone 22, a public switched telephone network (PSTN) modem 25, a facsimile machine (not shown), etc. The CP 20 may also include an xDSL communication device, such as an xDSL modem 23 that may permit a computer 24 to communicate with one or more remote networks via the CO 10. When a xDSL service is provided, a POTS filter 21 is interposed between the POTS equipment such as the telephone 22 and the twisted-pair telephone line 30. As is known, the POTS filter 21 includes a low-pass filter having a cut-off frequency of approximately 4 kilohertz to 10 kilohertz, in order to filter high frequency transmissions from the xDSL modem 23 and to protect the POTS equipment.
At the CO 10, additional circuitry is provided. Generally, a line card 18 (i.e., Line Card A) containing line interface circuitry is provided for electrically coupling a data transmission to the twisted-pair telephone line 30. In fact, multiple line cards 14, 18 may be provided (two shown for simplicity of installation) to serve a plurality of local loops. In the same way, additional circuit cards are typically provided at the CO 10 to handle different types of services. For example, an integrated services digital network (ISDN) interface card 16, a digital loop carrier line card 19, and other circuit cards supporting similar and other communication services, may be provided.
A digital switch 12 is also provided at the CO 10 and is configured to communicate with each of the various line cards 14, 16, 18, and 19. On the outgoing side of the CO (i.e., the side opposite the various local loops), a plurality of trunk cards 11, 13, and 15 are typically provided. For example, an analog trunk card 11, a digital trunk card 13, and an optical trunk card 15 are illustrated in FIG. 1. Typically, these circuit cards have outgoing lines that support numerous multiplexed DSL service signal transmissions.
Having introduced a conventional xDSL communication system 1 as illustrated and described in relation to FIG. 1, reference is now directed to FIG. 2, which is a prior art functional block diagram illustrating the various elements in a xDSL communications link 40 between a line card 18 located within a CO 10 and a xDSL modem 23 located at a CP 20. In this regard, the xDSL communications link 40 of FIG. 2 illustrates transmission of data from a CO 10 to a CP 20 via a twisted-pair telephone transmission line 30 as may be provided by a POTS service provider to complete a designated xDSL communications link 40 between a CO 10 and a CP 20. In addition, FIG. 2 further illustrates the transmission of data from the CP 20 to the CO 10 via the same twisted-pair telephone transmission line 30. With regard to the present illustration, data transmissions may be directed from the CP 20 to the CO 10, from the CO 10 to the CP 20 or in both. directions simultaneously. Furthermore, data transmissions can flow on the same twisted-pair telephone transmission line 30 in both directions, or alternatively on separate transmission lines (one shown for simplicity of illustration). Each of the separate transmission lines may be designated to carry data transfers in a particular direction either to or from the CP 20.
The CO 10 may include a line card 18 (see FIG. 1) that may comprise a CO-digital signal processor (DSP) 43, a CO-analog front end (AFE) 45, a CO-line driver 47 and a CO-hybrid 49. As illustrated in FIG. 2, the CO-DSP 43 may receive digital information from one or more data sources (not shown) and may send the digital information to a CO-analog front end (AFE) 45. The CO-AFE 45 interposed between the twisted-pair telephone transmission line 30 and the CO-DSP 43 may convert digital data, from the CO-DSP 43, into a continuous time analog signal for transmission to the CP 20 via the one or more twisted-pair telephone transmission lines 30.
One or more analog signal representations of digital data streams supplied by one or more data sources (not shown) may be converted in the CO-AFE 45 and further amplified and processed via a CO-line driver 47 before transmission by a CO-hybrid 49, in accordance with the amount of power required to drive an amplified analog signal through the twisted-pair telephone transmission line 30 to the CP 20.
As further illustrated in FIG. 2, a xDSL modem 23 located at a CP 20 may comprise a CP-DSP 42, a CP-AFE 44, a CP-line driver 46, and a CP-hybrid 48. The CP-hybrid 48, located at the CP 20, may de-couple a received signal from the transmitted signal in accordance with the data modulation scheme implemented by the particular xDSL data transmission standard in use. The CP-AFE 44, located at the CP 20, having received the de-coupled received signal from the CP-hybrid 48, may then convert the received analog signal into a digital signal, which may then be transmitted to a CP-DSP 42 located at the CP 20. Finally, the digital information may be further transmitted to one or more specified data sources such as the computer 24 (see FIG. 1).
In the opposite data transmission direction, one or more digital data streams supplied by one or more devices in communication with the CP-DSP 42 at the CP 20 may be converted by the CP-AFE 44 and further amplified via CP-line driver 46. The CP-hybrid 48, located at the CP 20, may then be used to couple the intended analog representations of the various digital signals to a transmit signal in accordance with the data modulation scheme implemented by the particular xDSL data transmission standard in use. As will be appreciated by those skilled in the art, the CP-line driver 46 may amplify and forward the transmit signal with the power required to drive an amplified analog signal through the twisted-pair telephone transmission line 30 to the CO 10. It is significant to note that the CP-hybrid 48 is used to regenerate the transmit signal so the transmit signal may be subtracted from the receive signal when the DSL is receiving. As a result, the CP-hybrid 48 does not affect the transmitted signal in any way. The CO-AFE 45 may receive the data from the CO-hybrid 49, located at the CO 10, which may de-couple the signal received from the CP 20 from the signal transmitted by the CO 10. The CO-AFE 45 may then convert the received analog signal into one or more digital signals, which may then be forwarded to the CO-DSP 43 located at the CO 10. Finally, the digital information may be further distributed to one or more specified data sources (not shown) by the CO-DSP 43.
Having briefly described a xDSL communications link 40 between the line card 18 located within the CO 10 and the xDSL modem 23 located at the CP 20 as illustrated in FIG. 2, reference is now directed to FIG. 3. In this regard, FIG. 3 is a prior art circuit schematic illustrating a conventional line driver 47. In communication systems designed to transmit data over metallic transmission lines, the line driver 47 is an amplifier which delivers the energy required to transmit the intended signal to the line via a back-matching resistor 70. Often impedance and voltage scaling is performed by coupling the output from the line driver 47 amplifiers to the transmission line 30 via a transformer 80.
The back-matching resistor 70 serves two purposes. First, the back-matching resistor 70 serves to match the impedance at the end of the transmission line 30. In order to provide a sufficient return loss, a resistor approximately equal to the line""s characteristic impedance 82 should terminate the line. Second, the back-matching resistor 70 permits the line driver 47 to simultaneously receive signals generated from a remote transmitter coupled to the transmission line 30 at the same time the line driver 47 is transmitting. The line driver 47 alone cannot terminate the transmission line 30 because the line driver 47 presents a low impedance to the remotely transmitted signal. The remotely transmitted signal may be recovered by subtracting from the voltage on the transmission line 30 the voltage introduced on the transmission line by the local transmitter. A hybrid amplifier 90 can perform the task of separating and recovering the remotely transmitted signal from the transmission line 30. Each of these elements is present in the circuit schematic of a prior art conventional line driver 47 as illustrated in FIG. 3.
As illustrated in FIG. 3, a differential signal input (i.e., Vin+xe2x88x92Vinxe2x88x92) to the conventional line driver 47 is fed into the input of a pre-amplifier stage, comprising pre-amps 60, 62 (herein labeled PRE-AMP A and PRE-AMP B). The pre-amplifier stage then feeds the high-power driver amplifiers 64, 66 (herein labeled DRIVER A and DRIVER B). The pre-amplifier stage, if implemented via complementary metal oxide semiconductor (CMOS) technology, would have nearly infinite input impedance. The outputs of the high-power driver amplifiers 64, 66 are loaded by the combination of the back-matching resistors 70, herein designated, Rt, in series with the line impedance 82, herein labeled, Zl.
As further illustrated in FIG. 3, the outputs of the high-power driver amplifiers 64, 66 are fed to a scaled version of the load via back-matching resistors 72, herein labeled, nRt and an emulated line impedance 84, labeled nZl in addition to being coupled to a load 100. The load 100 may comprise the transformer 80, the twisted-pair telephone transmission line 30, and the line impedance 82. The transmit signal generated across the emulated line impedance 84, nZl, is subtracted from the combined receive and transmit voltage appearing at the primary of the transformer 80 by a hybrid amplifier 90. As further illustrated in FIG. 3, the output of the hybrid amplifier 90, VRxe2x88x92(xe2x88x92VR) should comprise the received signal from a remotely located transmitter after the transmit signal has been subtracted, or 2VR. The back-matching resistors 70 emulate the impedance of the transmission line 82 as seen looking into the primary of a transformer 80. For simplicity, the transformer 80 illustrated in the circuit of FIG. 3 has a 1:1 turns ratio. As a result Rt 70 approximates xc2xd Zl.
Having briefly described the operation of a prior art conventional line driver 47 as illustrated in the circuit schematic of FIG. 3, reference is now directed to FIG. 4, which illustrates a schematic view of the output stage of a CMOS line driver 200. The focus of FIG. 4 is on the core output stage of a prior art CMOS line driver 200. For ease of illustration and discussion, the pre-amplifier and high-power gain stages, the class A-B control stage, and the hybrid amplifier all typical elements of a line driver 47 are not illustrated. Those skilled in the art will appreciate and understand the operation and implementation of the circuitry required to realize the omitted portions of the line driver 47 and the hybrid 49. As a result, the omitted portions of the line driver 47 and the hybrid 49 need not be described herein in order to appreciate the current sink only line driver that will be introduced and described with regards to FIGS. 5 through 8.
As illustrated in FIG. 4, the output stage of a conventional CMOS line driver 200 may comprise a pair of PMOS (MP) and NMOS (MN) devices herein designated as AMP A OUTPUT STAGE and AMP B OUTPUT STAGE. The PMOS device may source current from a power supply (not shown) into the load 100 while the NMOS device on the other side of the transformer 80 sinks the same current from the load 100 into ground. The preceding stage, not shown in this simplified schematic, performs the input sensing, amplification, and the class A-B quiescent current cross over control for the illustrated output devices. The class A-B quiescent current control typically limits the current drawn from the non-active device to a significantly smaller value than the maximum current for the semiconductor device in order to increase efficiency. It is significant to note that the two amplifiers AMP A and AMP B work as a pair. The load 100 current flows from VDD through a MP device on one amplifier, through the load 100, and on to ground through a MN device on the opposite amplifier. One of the two amplifiers, AMPs A, B is required to source as much current as the other amplifier on the opposite side of the load 100 is required to sink. In addition, there is a significantly smaller class A-B current flowing through the other device in order to avoid excessive distortion introduced when switching between sinking and sourcing load current on each side of the conventional CMOS output driver 200. Those skilled in the art will appreciate that the amplifier configuration illustrated in FIG. 4 is commonly referred to as a push-pull amplifier.
In general, for most semiconductor technologies, it is significantly more difficult to source currents having a large magnitude than it is to sink currents having a large magnitude. For CMOS technology, the transconductance of a NMOS device is typically a factor of three larger than the transconductance of a PMOS device of the same size biased with the same current. Thus, if both a NMOS and a PMOS device have to handle a current of the same magnitude, the PMOS device would have to be three times as large as the NMOS device. For CMOS line driver architectures, the transconductance difference becomes a significant issue as the capacitive load seen by the preamplifier stage becomes unreasonably large if the line driver 47 (see FIGS. 2 and 3) needs to deliver a current of several hundred milli-amperes. As the capacitive load increases, the achievable speed of the line driver 47 is reduced. It is important to note that xc2xe of the capacitive load is introduced by the PMOS (MP) device.
The peak currents required using the conventional CMOS output driver 200 for various xDSL communication standards may be identified using the following formula:                                           I            p                    =                                                    PAR                2                                            V                p                                      *                          10                              (                                  PWR                  10                                )                                                    ,                            Eq.  1            
where Ip is the peak current in mA, PAR is the peak-to-average ratio for the encoding method associated with the xDSL standard, PWR is the power delivered to the line in dBm, and Vp is the single-ended peak voltage across the primary of the transformer 80. If 3 Vpp is applied across the transmission line 30 (an attainable peak-to-peak output signal voltage using a conventional 5 Volt CMOS line driver), the required peak current for HDSL2 (16.8 dBm pulse amplitude modulation (PAM), PAR=3.8) would be 461 mA. If the same 3 Vpp is applied across the transmission line 30, the required peak current for ADSL-CP (12.5 dBm discrete multi-tone (DMT); PAR=5.1) would be 308 mA. Likewise, the required peak current for ADSL-CO (20.5 dBm DMT; PAR=5.1) would be 1945 mA, clearly beyond the capabilities of currently available conventional 5 Volt CMOS line drivers, as conventional 5 Volt CMOS line drivers have a maximum output current typically in the 100 mA through 350 mA range.
A brief look at bipolar and BiCMOS semiconductor technologies may highlight some additional functional and economic reasons for designing away from a conventional push-pull amplifier. Both bipolar and BiCMOS semiconductor manufacturing technologies typically optimize vertical isolated NPN devices for high performance. Usually, little effort is expended developing a high performance PNP device. For most BiCMOS manufacturing processes and even some bipolar manufacturing processes, the only PNP available is a lateral PNP, which has a unity gain frequency more than 100 times lower than a NPN device. This makes the technology less than adequate if a PNP device is part of the signal path.
In addition, most BiCMOS processes do not incorporate a lateral vertical isolated PNP device due to the added masks required and the associated cost and complexity of constructing such a device. For example, manufacturing a vertical isolated PNP for a typical medium cost bipolar manufacturing process may entail a cost increase of about 30%. For a typical low cost BiCMOS semiconductor manufacturing process, a vertical isolated PNP may entail a cost increase of approximately 40%.
Accordingly, there is a need for an improved line driver configuration that relies more heavily on sinking output currents rather then sourcing output currents in order to meet the maximum power requirements for most xDSL applications.
In light of the foregoing, the invention is a circuit and a method for constructing a line driver capable of sinking output currents with NMOS devices that is not required to push or source a significant amount of current. An output stage comprising NMOS devices, or alternatively NPN bipolar semiconductor devices, may be capable of delivering up to 4 times the current with an integrated circuit footprint of a similar size than previous line drivers utilizing a push-pull circuit architecture. In addition, an output stage comprising NMOS or NPN devices may be capable of delivering the increased current with a similar capacitive load as that seen by preamplifiers in push-pull line driver architectures.
The improved line driver architecture of the present invention provides increased performance and enables more power delivered to the line by increasing the maximum output current for a given rate and distortion. An improved line driver output stage may comprise a first amplifier, a second amplifier, a first transformer, a second transformer, and a plurality of back-matching resistor networks. A second preferred embodiment of an improved output stage of a line driver may comprise a first amplifier, a second amplifier, a transformer, and a plurality of back-matching resistor networks. Both preferred embodiments may be implemented with CMOS and bipolar semiconductor devices, as well as, a combination of the two semiconductor technologies.
The present invention can also be viewed as providing a method for increasing the available signal transmit power along a transmission line. In its broadest terms, a method for increasing the available signal transmit power on a transmission line can be described as: applying a transmit signal to an input stage of an integrated line driver; amplifying the transmit signal in the output stage of a line driver using amplifier components selected from the group consisting of NMOS and NPN bipolar semiconductor devices in the output stage signal path; and applying the amplified transmit signal via a plurality of resistor networks to the transmission line.
Other features and advantages of the present invention will become apparent to one skilled in the art upon examination of the following drawings and detailed description. It is intended that all such additional features and advantages be included herein within the scope of the present invention, as defined by the claims.